High order surfaces are a well known technique within the computer graphics industry. Higher order surfaces or “patches” which are functions of polynomial equations typically define a set of control points that are used to describe the behaviour of a curved surface in terms of well known mathematical parametric relationships between a variable ‘t’ (for a curve that is plotted in two dimension) or two variables u, v (for a curve that is plotted in three dimensions) and the surface of a curve. FIG. 1 illustrates a Bezier patch which is a well known example of a high order surface type used within 3D computer graphics. A point P 100, on the Bezier surface 110 is defined by the function of the parametric coordinates u, v 120 (also known as the domain co-ordinates) and the corresponding control points ki,j 130,
      P    ⁡          (              u        ,        v            )        =            ∑              i        =        0            n        ⁢                  ∑                  j          =          0                m            ⁢                                                  Au              i                        ⁡                          (                              1                -                u                            )                                            n            -            i                          ⁢                                            Bv              j                        ⁡                          (                              1                -                v                            )                                            m            -            j                          ⁢                  k                      i            ,            j                              
Where A and B are constants defined as,
  A  =                              n          !                                      i            !                    ⁢                                    (                              n                -                i                            )                        !                              ⁢                          ⁢      and      ⁢                          ⁢      B        =                  m        !                              j          !                ⁢                              (                          m              -              j                        )                    !                    
It should be noted that values of P(u,v) lie within the hull 140 represented by the control points Ki,j 130. It should also be noted that this is only an example of one possible surface formulation and that there are many other possibilities.
Tessellation is a well known technique that subdivides a surface into a number of smaller adjoined surfaces lying on the plane of and within the boundaries of the original surface. FIG. 2 illustrates tessellation of the domain points for a Bezier patch using binary sub-division. The un-tessellated domain 200 with 16 domain points and 0.25 intervals on each axis represents the minimum number of points within a tessellated patch, this being the same as the number of points within a Bezier surface. One level of tessellation is applied at 210 resulting in a further set of domain points being generated at intervals that lie at the mid points between each adjacent pair of points of the original set of points. A second level of tessellation 220 introduces a further set midpoints between these points generated at 210. This process is repeated until a suitable desired level of tessellation is achieved, this being determined by the application. It should be noted that this approach represents one possible method from many and is presented here only as an example.
Microsoft's Dx11 application programming interface (API) introduces a programmable approach for implementing patches within a graphics hardware pipeline. FIG. 3 illustrates the pipeline required by the Dx11 API. A vertex shader stage 300 takes a set of individual control points for a patch and applies an arbitrary mathematical transform to these using programmable hardware in a manner well known to those skilled in the art. The transformed control points are then passed to a hull shader 310 which calculates tessellation factors for the edges of the patch and applies further application defined modifications to the transformed control points.
The edge tessellation factors for the patch are passed to a tessellation unit 320. The tessellation unit is split into two parts, domain tessellation and connectivity tessellation. Domain tessellation subdivides a patch into a number of points known as “domain” points based on the supplied tessellation factors in a similar manner to that described for FIG. 2 but using a specific approach as prescribed by the Dx11 API. Connectivity tessellation determines how the resulting “Domain” points are combined or connected to produces tessellated primitives. As with domain tessellation the method for implementing this is defined by Microsoft's Dx11 and will be familiar to those skilled in the art.
The tessellated domain points are passed to a domain shader 330 which combines them with the control points produced by the hull shader in a programmable manner. Typically the domain shader will apply a well known curved surface formulation such as a Bezier patch as described above with respect to FIG. 1. The resulting values may then be further modified using well known techniques such as displacement mapping. Displacement mapping is a technique in which the results of a high order surface tessellation are displaced by a height that is sampled from a texture map. Displacement mapping typically means that the points on a curved surface no longer reside within a readily definable “hull”.
Tile based rendering systems are well-known. These subdivide an image into a plurality of rectangular blocks or tiles. One way in which this is done and the subsequent texturing and the shading performed is shown schematically in FIG. 4. These techniques are well known.
Tile based rendering is generally split into two phases, the first of which is known as the geometry processing phase which performs the following operations.
Firstly, a primitive/command fetch unit 400 retrieves command and primitive data from a memory and passes this to a geometry shader 405. A clip/cull unit 410 and a projection unit 415 may be interposed between geometry shader 405 and tiling unit 420 The primitive and command data may be transformed into screen space using well-known methods.
This data is then supplied to tiling unit 420 which inserts object data from the screen space geometry into object lists 425 for each of a set of defined rectangular regions or tiles. A tile object list for each tile contains primitives that exist wholly or partially in that tile. A tile object list exists for every tile on the screen, although some object lists may have no data in them.
The second phase of tile based rendering is generally called the rasterisation phase which performs the following operations.
The object lists are fetched by a tile parameter fetch unit 430 which supplies them tile by tile to a hidden surface removal unit (HSR) 435 which removes surfaces which will not contribute to the final scene (usually because they are obscured by another surface). The HSR unit 435 processes each primitive in the tile and passes only data for visible pixels to a shading unit 445.
The shading unit 445 takes the data from the HSR 435 and uses it to fetch textures using the texture unit 440 and applies shading to each pixel within a visible object using well-known techniques. The shading unit 445 then feeds the textured and shaded data to an on chip tile buffer 450. As operations are applied to an on chip tile buffer external memory bandwidth associated with this is eliminated.
Once each tile has been completed, the resulting data is written to an external scene buffer 455.
The addition of a Dx11 programmable tessellation pipeline to a tile based rendering system means that it is not possible to tile patch data without first fully tessellating and applying displacement mapping of the type discussed above. This results in a significant growth in the memory and bandwidth requirements associated with the tiled screen space parameter lists 425.